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Si5040
Register 5. RxintStatus (Sticky Bits)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
refLOS
LOS
LOL
fifoErr
tpErrAlarm tpSyncLos
sqmAlarm
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 0000 0000
Bit
7
6
5
4
3
2
1
0
48
Name
Reserved
refLOS
LOS
LOL
fifoErr
tpErrAlarm
tpSyncLos
sqmAlarm
Function
Read returns zero.
Reference Clock LOS Interrupt.
A latched version of the refLOS alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Loss of Signal Interrupt.
A latched version of the LOS alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Loss of Lock Interrupt.
A latched version of the LOL alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Receiver FIFO Error Interrupt.
A latched version of the fifoErr alarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Test Pattern Generator/Checker Alarm Interrupt.
A latched version of the tpErrAlarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Test Pattern Checker Loss of Sync Interrupt.
A latched version of the tpSyncLos alarm status bit. An interrupt is generated if interrupts
are enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit.
The interrupt may be cleared by writing a zero to this bit position or by disabling inter-
rupts.
Signal Quality Monitor Alarm Interrupt.
A latched version of the sqmAlarm status bit. An interrupt is generated if interrupts are
enabled (intEnable = 1) and if not masked by the corresponding interrupt mask bit. The
interrupt may be cleared by writing a zero to this bit position or by disabling interrupts.
Rev. 1.3
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